SyReC Synthesizer: An MQT tool for synthesis of reversible circuits

Reversible circuits form the backbone for many promising emerging technologies such as quantum computing, low power/adiabatic design, encoder/decoder devices, and several other applications. In the recent years, the scalable synthesis of such circuits has gained significant attention. In this work, we present the SyReC Synthesizer, a synthesis tool for reversible circuits based on the hardware description language SyReC. SyReC allows to describe reversible functionality at a high level of abstraction. The provided SyReC Synthesizer then realizes this functionality in a push-button fashion. Corresponding options allow for a trade-off between the number of needed circuit signals/lines (relevant, e.g., for quantum computing in which every circuit line corresponds to a qubit) and the respectively needed gates (corresponding to the circuit's costs). Furthermore, the tool allows to simulate the resulting circuit as well as to determine the gate costs of it. The SyReC Synthesizer is available as an open-source software package at https://github.com/cda-tum/syrec as part of the Munich Quantum Toolkit (MQT).


Introduction
Reversible circuits belong to a class of emerging computing devices that realize invertible Boolean functions, i.e., functions in which each input pattern is mapped to a unique output pattern and vice versa. This reversible characteristic is essential for the development of many emerging technologies such as quantum computing [1], adiabatic circuits [2], [3], encoding and decoding devices [4], [5], verification [6], [7], as well as many others. Accordingly, the design and synthesis of reversible circuits received significant attention in the past. Originally, corresponding synthesis approaches primarily relied on a functional description provided at a low abstraction level such as truth tables [8], [9], ESOP-based representations [10], or decision diagrams [11], [12]. However, to efficiently design and realize complex applications, description means at higher levels of abstractions are crucial. Accordingly, researchers started the development of reversible Hardware Description Languages (HDLs) that allow for describing the intended functionality at a high level of abstraction while, at the same, ensuring the reversibility throughout the design [13], [14].
In this work, we present the SyReC Synthesizer, an open-source implementation of the synthesis approach for the reversible HDL SyReC [13]. The SyReC Synthesizer is a part of the Munich Quantum Toolkit (MQT) and provides two different synthesis schemes as proposed in [13], [15], [16] (each coming with certain advantages and disadvantages). The tool also provides an easy-to-use Graphical User Interface (GUI) for users to conveniently synthesize reversible circuits from corresponding SyReC descriptions.

Description and Features
The SyReC Synthesizer allows users to automatically synthesize reversible circuits from a high-level HDL description [15]. The proposed tool is mainly implemented in C++ and works on all major operating systems. Moreover, with the help of Python bindings, the tool provides an easy-to-use GUI which allows users to specify the desired functionality similar to a classical IDE. The tool can easily be installed (without any need for compilation) and started by running the following commands: pip install mqt . syrec syrec -editor # To start the SyReC editor GUI Afterwards, the tool accepts any HDL description following the SyReC grammar and syntax as described in detail in [15]. As an example, consider the SyReC program for a simple 2-bit Arithmetic Logic Unit (ALU) as shown in Figure 1. This ALU consists of an input signal op based on which either the sum or the difference of the inputs x1 and x2 is stored in the output signal x0. By clicking on the button, the tool automatically synthesizes the corresponding circuit. To this end, two complementary synthesis schemes are available:

Cost-aware synthesis:
In this synthesis scheme, additional circuit lines (representing circuit signals) are introduced to store the corresponding intermediate results of each operation-thereby providing the liberty to accordingly modify the circuit without having any effect on the original inputs. This results in a circuit description where the gate costs 1 are kept moderate at the expense of a substantially larger number of additionally needed circuit lines. Figure 2 depicts the circuit resulting for the SyReC ALU description from Figure 1 using this cost-aware synthesis scheme.

Line-aware synthesis:
In this synthesis scheme, the goal is to keep the number of additionally required circuit lines as small as possible. To this end, the corresponding intermediate results of each operation are computed and stored using one of the available circuit lines (rather than additional circuit lines). Afterwards, the inputs are recomputed with the help of the corresponding inverse operations (see [15] for details). As this substantially increases the number of required gates and, hence, the gate costs of the circuit, dedicated building blocks and re-writing as well as translation techniques [16]- [18] are additionally employed to keep this overhead in check. Figure 3 depicts the circuit resulting for the SyReC ALU description from Figure 1 using this line-aware synthesis scheme. Figure 3 clearly show the differences in the gate costs and the number of lines of the resulting circuits: While the line-aware synthesis scheme generates a circuit with no additional circuit lines, it is quite inefficient concerning the number of gates. Vice versa, the circuit generated by the cost-aware synthesis scheme keeps the number of gates moderate, but results in a substantial amount of additional circuit lines. Depending on the addressed technology, these differences can have a huge impact. In quantum computing, for example, the number of circuit lines corresponds to the number of qubits-a rather restricted resource. Thus, in this case, it is desirable to keep the number of additional circuit lines as small as possible. If this is not the case, the gate costs are obviously the primary objective and a larger number of circuit lines can easily be accepted. By providing both synthesis schemes, the SyReC Synthesizer allows users to choose the method that best fits the addressed technology.

Figure 2 and
In addition to that, the tool allows users to quickly evaluate the costs of the resulting circuits (by clicking the button) and offers a simulation method to check the resulting circuits' functionality (by clicking the button). Figure 2: ALU circuit resulting from cost-aware synthesis. Figure 3: ALU circuit resulting from line-aware synthesis

Impact Overview
Reversible circuits provide a main basis for many emerging technologies and promising applications. Prominent examples include, e.g., • quantum computing [1] in which building blocks and so-called oracles rely on reversible circuits, • adiabatic circuits that utilizes reversible computations as demonstrated, e.g., in [2], • encoders and decoders [4], [5] which can benefit from reversible circuits as they naturally realize one-to-one mappings, • verification, in which characteristics of reversible logic can be exploited as proposed in [6], [7], and • many more.
All these application areas would substantially benefit from reversible circuits that can be described and, afterwards, are realized in terms of Hardware Description Languages (HDLs)-lifting the design process to higher levels of abstraction. However, while research on HDL-based synthesis of reversible circuits has been conducted for many years, barely any software tools and methods are publicly available. Not only does this slow down the research progress (since it becomes increasingly hard to compare against existing methods), it also means that barely anyone can explore this new and vastly different paradigm of developing circuits and systems.
The SyReC Synthesizer has been developed to change this dire situation. To this end, it provides open-source implementations of several key components in the HDL-based synthesis flow: • A reference implementation of the SyReC grammar together with a corresponding parser.
• Implementations of the state-of-the-art cost-aware and line-aware synthesis methods described above.
• An easy-to-use GUI for specifying, synthesizing, simulating, and analyzing SyReC programs and the resulting circuit realizations.
As a result, the proposed tool lays the foundation for developing and incorporating even more methods for the design of reversible circuits and systems in a publicly-available software package. Furthermore, by exposing all functionality via an easy to use Python interface and distributing the tool as a (pre-compiled) Python package, reversible computing becomes way more accessible to a much broader audience.

Conclusions
In this paper, we presented the HDL-based reversible circuit synthesis tool SyReC Synthesizer which is part of the Munich Quantum Toolkit (MQT). The tool offers an easy-to-use GUI which allows users to conveniently specify SyReC descriptions and, afterwards, to automatically synthesize corresponding reversible circuits out of it. To this end, two different schemes focusing on gate costs and number of lines, respectively, are provided. The tool is available as an open-source software package at https://github.com/cda-tum/syrec. An elaborate description of the different synthesis schemes is available in [13], [15], [16].